The present invention relates to a fuzzy logic controller having a regulating memory for fuzzification, a regulating decoder and a minimum/maximum circuit for inference formation and a defuzzification circuit downstream of the minimum/maximum circuit.
A fuzzy logic controller of the generic type is known, for example, from the publication by Watanabe entitled "A VLSI Fuzzy Logic Controller with Reconfigurable, Cascadable Architecture" from the IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, April 1990, pages 376 to 382. The controller concerned is a fuzzy logic controller which may have an on-chip memory, the on-chip memory requiring a relatively large amount of storage space and consequently of chip surface area.